The present invention relates to a method and a circuit for clock recovery and data recovery from a data stream such as a data stream on a communication channel.
In communications between several devices connected to a communication channel, information and data are transmitted in the form of a data stream constituted by an alternation of values of a quantity between two or more levels. Typically, in digital transmission the communication signal alternatively takes two values (high and low, or “0” and “1”) with a given frequency. In general, the communication channel can be a bus on which transmission takes place through electrical signals, an optical channel on which transmission takes place by means of optical pulses, a radio channel, etc.
Transmission takes place at high speed through a sequence of high and low values (0 and 1) according to a transmission protocol. Some transmission modes, called “synchronous transmissions” require that the data bus is combined with an auxiliary communication line where the clock signal is transmitted. Devices connected to the transmission line use the line dedicated to the clock signal to synchronize their transmission and reception and to correctly interpret the main data stream. This technique is very robust but has the intrinsic disadvantage of requiring an additional line for the clock which in fact does not transmit important information. Other transmission modes, called “asynchronous transmissions”, do not require the presence of an auxiliary line for the clock signal. For these transmission modes, the clock signal must be recovered. Various techniques are adopted for clock recovery. The most common techniques are based on high speed sampling of the signal on the bus and subsequent decimation. Other techniques are based on phase locking of the signal on the communication channel by means of PLL (Phase Lock Loop) circuits, where a dummy clock signal generated internally by the devices that participate in communication is phased with the signal circulating in the communication channel. In this last process the data stream transmitted on the channel, is required to present a transition between at least two levels to correct any drift errors of the oscillator of the PLL circuit. An example of a clock recovery system is described in U.S. Patent Publication No. 2004/0146131.